1. Field of Invention
The present invention relates to a test-element-provided substrate suitable for a multi-layered substrate, particularly a TFT substrate, and a liquid crystal device, etc. using the substrate, a method of manufacturing the same, a substrate for an electro-optical device, an electro-optical device, and an electronic apparatus.
2. Description of Related Art
A liquid crystal device is constructed by sealing liquid crystal between two substrates which are made of glass substrates, quartz substrates, or the like. In the liquid crystal device, active elements, such as thin film transistors (hereinafter, “TFT”) and pixel electrodes are disposed in a matrix shape on the one substrate, and counter electrodes (transparent electrodes (ITO (Indium Tin Oxide))) are disposed on the other substrate. The optical properties of the liquid crystal layer sealed between both substrates are changed in accordance with image signals, so that image display can be implemented.
In an electro-optical device, such as an active matrix driving liquid crystal device using the active elements, the pixel electrodes and switching elements are disposed on the substrate (active matrix substrate) corresponding to the intersections of a plurality of scan lines (gate lines) and a plurality of data lines (source lines) which are arranged in transverse and longitudinal directions, respectively.
The switching elements, such as the TFT elements, are turned on by ON signals supplied to the gate lines, and the image signals which are supplied through the source lines are written into the pixel electrodes (transparent electrodes (ITO)). In this way, voltages are applied to the liquid crystal layer between the pixel electrodes and the counter electrodes based on the image signals, whereby the arrangement of the liquid crystal molecules can be changed. By doing so, the transmittance of each pixel is changed, so that the image display can be implemented by changing the light components that pass though the image electrodes and the liquid crystal layer in accordance with the image signals.
In the case where elements constituting an element substrate, such as the TFT substrate, are provided in one plane on the substrate, the occupied area of the elements is increased and the area of the pixel electrodes is reduced, so that the pixel opening ratio may be lowered. Therefore, for a laminated structure adapted in the prior art, elements are separately formed in the respective one of plural layers, and the interlayer insulating films are disposed among the layers (film formation layers) to electrically insulate the film formation layers.
In other words, the element substrates are constructed by laminating film formation layers, such as semiconductor thin films, insulating thin films, and conductive thin films having predetermined patterns on the glass substrate or quartz substrate. The TFT substrate is formed by repeatedly performing film formation processes of various films and photolithography processes on each of the film formation layers. For example, on the TFT substrate, film formation layers, such as semiconductor layers constituting channels of the TFT elements, wiring layers for data lines, and pixel electrode layers made up of ITO film are laminated.
In some cases, on the element substrate, patterns of test elements (hereinafter, referred to as test-element-pattern) referred to as TEG (test element group) may be provided besides the film formation patterns for the device itself. The test elements are provided for the purpose of measuring yield of the device after it has been manufactured, solving problems associated with the deterioration of device performance, and measuring transistor characteristics, contact resistance, or the like. For example, each of the test element patterns having the same structure as an element group including transistors, contact holes, and wiring of each of the pixel regions is provided outside each of the pixel regions, whereby testing for the test element patterns is performed to manage the processes.
In addition, the test element patterns are provided to obtain the characteristics from a surface of the device through pads, specifically, output terminals that are provided in the film formation layers of test element formation regions.
However, a surface of the laminated structure of the film formation layers may have uneven portions depending on the film formation patterns of the respective layers. In the case where such uneven portions occur on layers contacting the liquid crystal layer, alignment failure of the liquid crystal may easily occur. Therefore, in some cases, a planarization process is performed to planarize an interlayer insulating film below a layer near the liquid crystal layer. For example, the interlayer insulating film below each of the pixel electrode layers is polished to be planarized by the so-called CMP (Chemical Mechanical Polishing) process.
In the case where the CMP process is not performed, variations in the film thicknesses of the respective layers are within about 5%, whereas in the case where the CMP process is performed, the film thicknesses in some portions of the interlayer insulating film changes remarkably depending on the unevenness from the film formation patterns. In this case, the variations in the film thicknesses are increased up to 20 to 30%. If so, in some cases, pads (hereinafter, referred to as a deep PAD) formed on a layer just below a thin interlayer insulating film and pads (hereinafter, referred to as a shallow PAD) formed on a layer just below a thick interlayer insulating film may have two different distances from the surface of the device. Therefore, in the case where an interlayer insulating film is removed by an etching process in order to expose two pads to test characteristics of the test element, if only an etching process is performed, a contact hole may be formed in the only shallow PAD, but a contact hole may not be completely opened in the deep PAD. However, if an over-etching process is performed to open the contact hole in the deep PAD, the shallow PAD may be entirely etched and removed. Specifically, there is a problem that, since depths of pads are different depending on the CMP processes, contact holes reaching two respective pads may not be opened by one process.
An approach of providing contact holes in the test element formation regions has been considered in the related art in order to measure the contact resistances of the contact holes in the device. The other contact holes corresponding to the contact holes in the device are provided in the test element formation regions. Even in this case, if the CMP process does not implement planarization, the contact resistances of the contact holes in the device can be estimated by measuring the contact resistances of the other contact holes in the test element formation regions.
However, in the case where the planarization is implemented by the CMP process, depending on the film formation patterns of the respective layers, the locations (depths) of the contact holes in the device with reference to the surface of the device and the depths of the other contact holes formed in the test element formation regions may be different, which presents another problem in that the contact resistances of the contact holes in the device cannot be estimated even by measuring the contact resistances of the other contact holes of the test element formation regions.